Navigation Bar e-mail me!

Updated 10/3/08

SystemVerilog Errata

SystemVerilog for Verification, Second Edition, Errata

Thank you to everyone who has sent me the mistakes they found in my book, SystemVerilog for Verification, first edition. Like a hardware project, the book has "bugs". Both hardware and books should be verified by someone other than the person who created it. Now if I can only figure out how to perform constrained random testing of text...

This page will show any functional mistakes in the SECOND EDITION of the book. Code that does not work, explanations that are incorrect, etc. Simple typos and bad English are not included. The apostrophes point left and right in some examples - blame FrameMaker!

Remember - if you are the first to find a mistake in a chapter, you get a free, autographed copy. There are 12 chapters, so that is 12 copies. This offer is open only to residents of the USA, as overseas shipping is too high. You must have a legal copy of the book.

Chapter 1 Verification Guidelines

None

Chapter 2 Data Types

  • Page 30, Sample 2.9, the fourth-to-last line should be:
    md = ’{’{9, 8, 7}, ’{3{    32’d5}}};
  • Page 32, Sample 2.13, the last three lines should be:
      $display("src[1:4] %s dst[1:4]",
               (src[1:4] == dst[1:4]) ? "==" : "!=");
    end
  • Page 60, Sample 2.53, in the 6th to last line, shortened the task name to:
    my_log($psprintf("%s %5d", s, 42));

Chapter 3 Procedural Statements and Routines

  • Page 75, Sample 3.25:
    logic [7:0] local_addr;
    local_addr = addr << 2; // Bug     solved

Chapter 4 Connecting the Testbench and Design

  • Page 105 and 106, Sample 4.32. Module instances outside of a module are not legal according to the latest interpretation of the LRM, so the explanation at the bottom of 105 and sample 4.32 are very different.

    "Sample 4-32 shows a program that is instantiated in a module that is implictly instantiated in the top-level scope. The program can use a relative or absolute reference to the clk signal in the module. You may want to use a macro to hold the hierarchical path so that when the path changes, you only have to change one piece of code."
    Sample 4.32 Cross-module references with $root
    `timescale 1ns/1ns
    parameter TIMEOUT = 1_000_000;

    module top;
      bit clk;
      test t1(.*);
    endmodule

    `define TOP $root.    top
    program automatic test;
      initial begin
        // Absolute reference
        $display("clk=%b", $root.    top.clk);
        $display("clk=%b", `TOP.clk);    // With macro

        // Relative reference
        $display("clk=%b",     top.clk);
        end
    endprogram

    Chapter 5 Basic Object Oriented Programming

  • Page 133, section 5.7, swapped words. The sentence should read:
    A SystemVerilog handle can only point to objects of one type, so they are called "type-safe."
  • Page 152, Sample 5.30, misspelling in second comment:
    // Construct a new Statistics object
  • Page 155, Sample 5.35, wrong copy on line 5!
    dst = src.copy();

    Chapter 6 Randomization

  • Page 193, Sample 6.40, need to include the class definition in the program block.
    // test.sv
    program     automatic test;
    `include "packet.sv"
    constraint Packet::c_external {length == 1; }
    ...

    Chapter 7 Threads and Interprocess Communication

    None

    Chapter 8 Advanced Object Oriented Programming and Testbench Guidelines

    None

    Chapter 9 Functional Coverage

    Page 321, Section 9.7.2, final line:
    other values, 1 or 3, are not seen.

    Chapter 10 Advanced Interfaces

    None

    Chapter 11 A Complete SystemVerilog Testbench

    None

    Chapter 12 Interfacing with C

    • Page 383, Sample 12.4, the second line should be:
      output int sum      );

    References

    • Page 421, the VMM was copyright 2006, even though it was published in 2005.

    Credits

    Thanks to Tony Hsu, Brian Jensen, Eric Ohana, Dan Shupe, and Randy Wetzel for their help.
    Home SystemVerilog OpenVera PLI Verilog Verification PMC Emacs Bicycling Personal Viewlogic