SystemVerilog Errata

SystemVerilog for Verification, Second Edition, Errata

Thank you to everyone who has sent me the mistakes they found in my book, SystemVerilog for Verification, first edition. Like a hardware project, the book has "bugs". Both hardware and books should be verified by someone other than the person who created it. Now if I can only figure out how to perform constrained random testing of text...

This page will show any functional mistakes in the SECOND EDITION of the book. Code that does not work, explanations that are incorrect, etc. Simple typos and bad English are not included. The apostrophes point left and right in some examples - blame FrameMaker!

Remember - if you are the first to find a mistake in a chapter, you get a free, autographed copy. There are 12 chapters, so that is 12 copies. This offer is open only to residents of the USA, as overseas shipping is too high. You must have a legal copy of the book.

Chapter 1 Verification Guidelines

None

Chapter 2 Data Types

• Page 29, Sample 2.7, the last line should be:
  descend = '{default:1}; // Sets all elements to 1 Also, delete the last sentence of the previous paragraph.
• Page 30, Sample 2.9, the fourth-to-last line should be:
  md = ’{’{9, 8, 7}, ’{3{32’d5}}};
• Page 32, Sample 2.13, the last three lines should be:
    $display("src[1:4] %s dst[1:4]",
             (src[1:4] == dst[1:4]) ? "==" : "!=");
  end
• Page 35, the paragraph after Sample 2-17 should say:
  Line F allocates 20 new elements, and copies the existing 5 elements of dyn to the beginning of the array.
• Page 39, Sample 2.21, the first few lines should be:
  initial begin
     bit [63:0] assoc[bit [63:0]], idx = 1;
• Page 55, Section 2.12:
  Before enumerated types, you had to use text macros. Their global scope is too broad, and, in most cases, are not visible in the debugger.
• Page 57, the third to last sentence should read:
  This is similar to a for-loop that tries to step through the values 0 to 3 with an index declared as bit [1:0].
• Page 58, Sample 2.51, the second to last line should be:
  $display("C2 is %0d / %s", c2, c2.name);
• Page 60, Sample 2.53, in the 6th to last line, shortened the task name to:
  my_log($psprintf("%s %5d", s, 42));

Chapter 3 Procedural Statements and Routines

• Page 70, Sample 3.12, second to the last line should be:
    $display("The array checksum is %0d", checksum);
• Page 75, Sample 3.25:
  logic [7:0] local_addr;
  local_addr = addr << 2; // Bug solved

Chapter 4 Connecting the Testbench and Design

• Page 87: ignore the [Au3] note in the right margin.
• Page 91, Sample 4.15, the nineth line should be:
    assign ifc.w = local_wire;
• Page 105 and 106, Sample 4.32. Module instances outside of a module are not legal according to the latest interpretation of the LRM, so the explanation at the bottom of 105 and sample 4.32 are very different.
  
  "Sample 4-32 shows a program that is instantiated in a module that is implictly instantiated in the top-level scope. The program can use a relative or absolute reference to the clk signal in the module. You may want to use a macro to hold the hierarchical path so that when the path changes, you only have to change one piece of code."
  Sample 4.32 Cross-module references with $root
  `timescale 1ns/1ns
  parameter TIMEOUT = 1_000_000;
  
  module top;
    bit clk;
    test t1(.*);
  endmodule
  
  `define TOP $root.top
  program automatic test;
    initial begin
      // Absolute reference
      $display("clk=%b", $root.top.clk);
      $display("clk=%b", `TOP.clk);    // With macro
  
      // Relative reference
      $display("clk=%b", top.clk);
      end
  endprogram
  

Chapter 5 Basic Object Oriented Programming

• Page 133, section 5.7, swapped words. The sentence should read:
  A SystemVerilog handle can only point to objects of one type, so they are called "type-safe."
• Page 149, Sample 5.25, last line should be:
  endfunction // create
• Page 152, Sample 5.30, misspelling in second comment:
  // Construct a new Statistics object
• Page 155, Sample 5.35, wrong copy on line 5!
  dst = src.copy();

Chapter 6 Randomization

• Page 167, last paragraph, second sentance should read:
  In Sample 6.2, since there are no random variables, randomize() just checks the value of age to see if it is in the bounds specified by the constraint c_teenager.
• Page 171, Sample 6.10, the last two constraints are missing ']':
  b inside ([$:4], [20:$]}; // 0 <= b <= 4 || 20 <= b <= 127
  e inside ([$:4], [20:$]}; // 0 <= b <= 4 || 20 <= b <= 63
  
• Page 188, Sample 6.34, first line should be:
  typedef enum {READ8, READ16, READ32} read_e;
• Page 193, Sample 6.40, need to include the class definition in the program block.
  // test.sv
  program automatic test;
  `include "packet.sv"
  constraint Packet::c_external {length == 1; }
  ...

Chapter 7 Threads and Interprocess Communication

• Page 236, Sample7.26, the 3rd to last line should not have () as triggered is an event property, not a method:
  wait(gen_done.triggered); // Wait for finish
• Page 249, Sample 7.41, after the class declaration:
    endclass : Consumer
  
    Producer p;
    Consumer c;
  
• Page 250, Sample 7.43, add some declarations:
  program automatic mbx_evt;
  mailbox mbx;
• Page 251, Sample 7.44, after the class declaration:
    endclass : Consumer
  
    Producer p;
    Consumer c;
  
  initial begin
      mbx = new();
• Page 252, Sample 7.46, same as previous:
    endclass : Consumer
  
    Producer p;
    Consumer c;
  
  initial begin
      mbx = new();
      rtn = new();

Chapter 8 Advanced Object Oriented Programming and Testbench Guidelines

• Page 282, second to last paragraph. The original wording is unclear, so try the following:
  OOP languages such as SystemVerilog have two constructs to allow you to build a shareable base class. The first is an abstract class, which is a class that can be extended, but not instantiated directly. It is defined with the virtual keyword. The second is a pure virtual method, which is a prototype without a body. A class extended from an abstract class can only be instantiated if all virtual methods have bodies. The pure keyword specifies that a method declaration is a prototype, and not just an empty virtual method. Lastly, pure virtual methods can only be declared in an abstract class. An abstract class can contain pure virtual methods, virtual methods with and without a body, and non-virtual methods. Note that if you define a virtual method without a body, you can call it, but it just immediately returns.
• Page 288, Sample 8.32, the correct scoreboard function should be save_expected:
    function void save_expected(input Transaction tr);

Chapter 9 Functional Coverage

• Page 321, Section 9.7.2, final line:
  other values, 1 or 3, are not seen.

Chapter 10 Advanced Interfaces

None

Chapter 11 A Complete SystemVerilog Testbench

• Page 357, sample 11-6, the 14th line should be:
  cfg = new(numRx, numTx);
  Otherwise this is accessing program-level parameters instead of local variables.

Chapter 12 Interfacing with C

• Page 383, Sample 12.4, the second line should be:
  output int sum);
• Page 387, last paragraph, change the third sentance to:
  If you need more than one instance of a module that calls C code, the C code needs to store its variables somewhere other than in static variables.
• Page 402, section 12.5.3, remove the sentence:
  In Sample 12.24, the C code assumed that the array had five elements, numbered 0.4.

References

• Page 421, the VMM was copyrighted 2006, even though it was published in 2005.

Credits