SystemVerilog for Verification Errata

Last updated 12/11/07

Thank you to everyone who has sent me the mistakes they found in my book, SystemVerilog for Verification, first edition. Like a hardware project, the book has "bugs". Both hardware and books should be verified by someone other than the person who created it. Now if I can only figure out how to perform constrained random testing of text...

As of September 2006 I have sent out books to all the people who were the first to find mistakes in each of the chapters. Don't worry, I am already working on the second edition, giving you more opportunity to earn a free book.

A revised first edition came out June 2007 that fixed many of the errata shown below.

The following list shows larger mistakes in the book. Minor typos and poor English are not listed.


Chapter 1 Verification Guidelines

Chapter 2 Data Types

Chapter 3 Procedural Statements and Routines

Chapter 4 Basic OOP

Chapter 5 Connecting Testbench and Design

Chapter 6 Randomization

Chapter 7 Threads and Interprocess Communication

Chapter 8 Advanced OOP and Guidelines

Chapter 9 Functional Coverage

Chapter 10 Advanced Interfaces


Thanks to Veerendra Bharg Alluri, Steve Barrett, Shalom Bresticker, John Brooks, Heath Chambers, Keith Chan, Luke Chang, Haihui Chen, Gunther Clasen, Steve Collins, Hashem Heidaragha, Louis Hsiao, Tony Hsu, Stefan Kruepe, Jimnan Kuo, Jim Lewis, Frank Lin, Daguang Liu, Victor Lopez, Michael Macheski, Robin van Malenhorst, Ronald Mehler, Mike Mintz, Thinh Ngo, John Nolan, Ben Rahardja, Afroza Rahman, Chandrasekar Rajanayagam, Jonathan Schmidt, Dhaval Shah, Chandru Sippy, Dave Snogles, Mladen Stanic, Raymond Sylvestre, Hugh Walsh, Larry Widigen, Cuihong Zhao, and Chunlin Zhang for their help.