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Updated 8/3/11

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SystemVerilog for Verification, second edition

SystemVerilog for Verification, second edition - Book Cover This book is an introduction to the testbench features of the SystemVerilog language. It is meant for anyone who knows basic Verilog (1995) and needs to verify a design. It includes over 400 examples! You can order it from Amazon or Springer

Book description

SystemVerilog for Verification, second edition, teaches the reader how to use the power of the new SystemVerilog testbench constructs plus guidelines explaining why to choose one style over another. The book clearly explains the concepts of Object Oriented Programming, Constrained Random Testing, and Functional Coverage. The book covers the SystemVerilog verification constructs such as classes, program blocks, randomization, and functional coverage. SystemVerilog for Verification also reviews design topics such as interfaces and array types. There are over 400 code samples and detailed explanations. Learn the inner workings of such concepts as polymorphism, callbacks, and factory patterns. In addition, the book includes hundreds of guidelines to make you more productive with the language, and also explanations for common coding mistakes so you can avoid these traps. The book is based on Synopsys courses, seminars, and tutorials that Chris Spear developed for SystemVerilog, Vera, RVM, and OOP. SystemVerilog for Verification focuses on the best practices for verifying your design using the power of the language.

What is new in the second edition?

This new edition of SystemVerilog for Verification has many improvements over the first edition that was published in 2006.
  • The anticipated 2009 version of the SystemVerilog Language Reference Manual (LRM) has many changes, both large and small. This book tries to include the latest relevant information.
  • Many readers asked me for more details on SystemVerilog concepts. Almost all of these conversations have been incorporated into this book as expanded explanations and code samples. Starting with chapter 2, nearly every paragraph and example has been rewritten, revised, or just tweaked. There are over 50 new pages in the original ten chapters, and over 70 new examples. In all, the new edition is almost 1/3 larger than the original.
  • You asked for more examples, especially large ones. This edition has a directed testbench at the end of Chapter 4, and complete constrained random testbench in Chapter 11.
  • Not all testbench code is written in SystemVerilog, so I added Chapter 12 to show how to connect C and C++ code to SystemVerilog with the Direct Programming Interface.
  • Most engineers read a book starting with the index, so I doubled the number of entries. We also love cross references, so I have added more so you can read the book non-linearly.
  • Lastly, a big thanks to all the readers who spotted mistakes in the first edition, from poor grammar to code that was obviously written on the morning after a 18-hour flight from Asia to Boston. This edition has been checked and reviewed many times over, but once again, all mistakes are mine.

Sneak Peek

Take a peek at the book. Here are the first pages of each chapter, plus the full table of contents, index, list of examples, and figures.

Code Examples

Here are a few code examples from the book.
  • arb_if The arbiter example from Chapter 5.
  • uniquearray The unique array example from Chapter 6.
  • atm_virt_if The ATM switch with virtual interfaces, from Chapter 10.
  • multi_virt_if_port The multiple virtual interface example from Chapter 10, which passes an array of virtual interfaces through a port.
  • multi_virt_if_xmr The multiple virtual interface example from Chapter 10, which passes an array of virtual interfaces through a cross-module reference.
  • Utopia Chapter 11 shows a complete SystemVerilog testbench for an ATM design. Here is the complete testbench and code, ready to run.
  • Sockets Chapter 12 covers the DPI (Direct Procedural Interface), an easy way to connect C code to SystemVerilog. This example is for a client-server system using sockets to connect a C program to a simulation.

Tricks and Techniques

Vera allowed the user to reserve regions of values, but this did not make it into the SystemVerilog language. Download the Region package, rewritten for SystemVerilog.


On Design Radio podcast with Chris Spear Listen to the podcast from On Design Radio, featuring an interview with me about the book. Click on the triangle at the bottom of the description to listen.

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