Updated 2/1/07
Verification Page
This book is an introduction to the testbench features of the
SystemVerilog language. It is meant for anyone who knows basic
Verilog (1995) and needs to verify a design. It includes over 300
examples! You can order it from Amazon
or Springer.
The best overall methodology book out there is Janick Bergeron's very useful new
book Writing Testbenches with SystemVerilog The 2.5
edition now covers has great overview of verification mthodology and a
brief introduction to the SystemVerilog testbench constructs. Read
more about this book at
Janick's web site.
A more specific methodology guide is the Verification Methodology Manual for SystemVerilog
by Janick Bergeron, Ed Cerney, Alan Hunter, and Andrew Nightingale. This book
contains rules for building a complete verification environment.
Janick also run the Verification Guild which is a great resource for exchanging ideas on Verification.
While not specifically dedicated to verification, John Cooley's ESNUG is a good source of information
on all EDA tools. Always controversial, often raving, get the real
dirt from the sheep farmer.
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