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Updated 1/2/08

Verilog Page

A Brief History

The Verilog language was created by Phil Moorby at Gateway Design Automation in the mid-1980's. The company was aquired by Cadence Design Systems on January 2nd, 1990 (the same day I started with them). Gateway had kept Verilog propriatary but Cadence, wanting to gain an edge on VHDL in the language wars, opened it up by donating it to the IEEE. The first version of the 1364 standard was approved in 1995, and the second in 2001.

The changes from 1995 to 2001 were slow in coming and only incremental. Several EDA and design companies realized they needed to accelerate the process, or else Verilog-2007 was going to be too little, too late. So Accellera was formed, starting with the donation of SUPERLOG from Co-Design, later aquired by Synopsys. The synthesizable constructs were turned into SystemVerilog 3.0. (1.0 was Verilog-1995, and 2.0 was Verilog-2001.) This was standardized June 2002.

Meanwhile, on the testbench front, Synopsys donated OpenVera, Cadence donated Sugar, and SUPERLOG continued to supply inspiration. Accellera is working on SystemVerilog 3.1 and hopes to finish the specification by DAC 2003. At some point all this will be given to the IEEE to add to the 1364 standard.

The end result of all of this will be a new standard allowing higher level design, testbenches, and assertions all in one language, and soon enough to be relevant.

For more information

To learn more about SystemVerilog, check out classes from Synopsys, Stu Sutherland, or Cliff Cummings.

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