Navigation Bar e-mail me!

Updated 2/29/12

SystemVerilog Page

SystemVerilog for Verification, third edition

SystemVerilog for Verification, third edition - Book Cover This book is an introduction to the testbench features of the SystemVerilog language. It is meant for anyone who knows basic Verilog (1995) and needs to verify a design. It includes over 500 examples! You can order it from Amazon or Springer. It was written by Chris Spear and Greg Tumbush.

Book description

SystemVerilog for Verification, third edition, teaches the reader how to use the power of the SystemVerilog testbench constructs plus guidelines explaining why to choose one style over another. The book clearly explains the concepts of Object Oriented Programming, Constrained Random Testing, and Functional Coverage. The book covers the SystemVerilog verification constructs such as classes, program blocks, randomization, and functional coverage. SystemVerilog for Verification also reviews design topics such as interfaces and array types. There are over 500 code samples and detailed explanations. Learn the inner workings of such concepts as polymorphism, callbacks, and factory patterns. In addition, the book includes hundreds of guidelines to make you more productive with the language, and also explanations for common coding mistakes so you can avoid these traps. The book is based on Synopsys courses, seminars, and tutorials that Chris Spear developed for SystemVerilog, UVM, VMM, and OOP. Plus Greg Tumbush has contributed homework questions from his college course on verification. SystemVerilog for Verification focuses on the best practices for verifying your design using the power of the language.

What is new in the third edition?

This new edition of SystemVerilog for Verification has many improvements over the second edition that was published in 2008. The biggest change is that this edition can also be used as a textbook for an undergraduate or graduate course in verification of digital designs.
  • The anticipated 2012 version of the SystemVerilog Language Reference Manual (LRM) has many changes, both large and small. This book tries to include the latest relevant information.
  • Once again, Chris and Greg have responded to feedback from readers, professors, and students about SystemVerilog concepts. Almost all of these conversations have been incorporated into this book as expanded explanations and code samples. Starting with chapter 2, most pages have been improved with clearer explanations and better code samples. There are over 40 new pages with new information on UVM concepts such as factory patterns.
  • Most engineers read a book starting with the index, so once again I doubled the number of entries. We also love cross references, so I have added more so you can read the book non-linearly.
  • Lastly, a big thanks to all the readers who spotted mistakes in the first edition, from poor grammar to code that was obviously written on the morning after a 18-hour flight from Asia to Boston. This edition has been checked and reviewed many times over, but once again, all mistakes are mine and Greg's.

Sneak Peek

Take a peek at the book. Here are the first pages of each chapter, plus the full table of contents, index, list of examples, and figures.

Code Examples

Here are a few code examples from the book.
  • arb_if The arbiter example from Chapter 5.
  • uniquearray The unique array example from Chapter 6.
  • atm_virt_if The ATM switch with virtual interfaces, from Chapter 10.
  • multi_virt_if_port The multiple virtual interface example from Chapter 10, which passes an array of virtual interfaces through a port.
  • multi_virt_if_xmr The multiple virtual interface example from Chapter 10, which passes an array of virtual interfaces through a cross-module reference.
  • Utopia Chapter 11 shows a complete SystemVerilog testbench for an ATM design. Here is the complete testbench and code, ready to run.
  • Sockets Chapter 12 covers the DPI (Direct Procedural Interface), an easy way to connect C code to SystemVerilog. This example is for a client-server system using sockets to connect a C program to a simulation.

Tricks and Techniques

Vera allowed the user to reserve regions of values, but this did not make it into the SystemVerilog language. Download the Region package, rewritten for SystemVerilog.




Home SystemVerilog OpenVera PLI Verilog Verification PMC Emacs Bicycling Personal Viewlogic